The project started with my Erasmus experience in Valencia. During the exchange period, I had the chance to attend a course and get hands-on experience with FPGA and the related development tools.

The following year I started the master thesis at Universidad Politecnica de Valencia (UPV) in collaboration with Politecnico di Milano. It consisted in the design and VHDL implementation of a Reed-Solomon decoder.

Publications

The study was presented at Digital System Design (DSD) 2018 Conference; the full text can be downloaded here. The detailed agenda is available at this URL.

Moreover, the research track lead to a scientific article published on Springer Circuits, Systems, and Signal Processing (CSSP).